ISL89162FBEBZ【PDF 5/14 页】IC MOSFET DRIVER 2CH 6A 8SOIC

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ISL89160, ISL89161, ISL89162

DC Electrical Specifications V DD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over

the operating junction temperature range, -40°C to +125°C. (Continued)

T J = +25°C

T J = -40°C to +125°C

MIN

MAX

PARAMETERS

Input Bias Current

for INA, INB

SYMBOL

I IN

TEST CONDITIONS

GND < V IN < V DD

MIN

TYP

MAX

(Note 7)

-10

(Note 7)

+10

UNITS

μA

OUTPUTS

High Level Output Voltage

Low Level Output Voltage

V OHA V OHB

V OLA V OLB

V DD - 0.1

GND

V DD

GND + 0.1

Peak Output Source Current

Peak Output Sink Current

I O

V O (initial) = 0V, C LOAD = 10nF

V O (initial) = 12V, C LOAD = 10nF

-6

NOTES:

7. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.

8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic

capacitance.

9. A 400μs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9

10. The true state of a specific part number is defined by the input logic symbol.

11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted

inputs is less than the logic 0 threshold voltage.

AC Electrical Specifications V DD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits apply over

the operating junction temperature range, -40°C to +125°C.

T J = +25°C

T J = -40°C to +125°C

PARAMETERS

Output Rise Time (see Figure 4)

Output Fall Time (see Figure 4)

Output Rising Edge Propagation Delay for

Non-Inverting Inputs (see Figure 3)

Output Rising Edge Propagation Delay with Inverting

Inputs (see Figure 3)

Output Falling Edge Propagation Delay with

Non-Inverting Inputs (see Figure 3)

Output Falling Edge Propagation Delay with Inverting

Inputs (see Figure 3)

Rising Propagation Matching (see Figure 3)

Falling Propagation Matching (see Figure 3)

Miller Plateau Sink Current

(See Test Circuit Figure 5)

SYMBOL

t R

t F

t RDLYn

t RDLYi

t FDLYn

t FDLYi

t RM

t FM

-I MP

TEST CONDITIONS

C LOAD = 10nF,

10% to 90%

C LOAD = 10nF,

90% to 10%

No load

V DD = 10V,

V MILLER = 5V

V DD = 10V,

V MILLER = 3V

V DD = 10V,

V MILLER = 2V

MIN

TYP

4.7

3.7

MAX

MIN

MAX

UNITS

FN7719.3

February 20, 2013

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